ALPS: An Automatic Layouter for Pass-Transistor Cell Synthesis
نویسندگان
چکیده
The layout s y n t h e s i s for pass transistor c e l l s (PTCs) i s different from that for CMOS c e l l s because o f the various s i z e s o f transistors used in a PTC and the imbalance i n the number o f pMOS and nMOS transis tors . This makes i t d i f f icult t o app ly c o m m o n l y used l inear transistor placement t o PTC layout . Moreover, the mixed placement with CMOS cel ls restricts the layout freedom o f PTCs. Therefore a sandwiched selector structure and pass-transistor graph search are proposed for enab l ing a multi-row transistor layout and an e f f i c i en t search algorithm for the di f fus ion layer sharing problem. Pass-transistor c e l l s generated b y ALPS (automatic l ayouter for pass-transistor c e l l s y n t h e s i s ) are confirmed t o have a lmos t the same area dens i ty as that o f manual ly des igned ce l l s .
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تاریخ انتشار 1998